As the integration degree of the semiconductor memories becomes higher, problems are raised in connection with lowering of breakdown voltage of semiconductor devices, attendant on miniaturization, and also in connection with increasing current consumption. For combating the problem, attempts are being made to lower the power supply voltage. In a DRAM (Dynamic Random-Access Memories), it is felt to be necessary to lower the array voltage in order to cope with the lowered breakdown voltage of the elements making up the memory cells, such as capacitors.
However, the lowering of the array voltage is retrogressive from the viewpoint of raising the speed of the sensing operation and hence poses a problem. As a countermeasure, a so-called overdrive system has been developed, in which the memory cell array is driven at a high voltage only during an initial period of the sensing operation.
FIG. 13 is a circuit diagram showing essential portions of a DRAM having typical conventional sense amplifier of the overdrive system. The array of the state-of-the-art DRAM is made up of units termed banks, each of which is made up of a plural number of sub-arrays A, B, . . . , each including the same number of sense amplifiers and the same number of memory cells. FIG. 13 shows one of such banks. The sub-array A of the bank shown includes an overdrive circuit 1, a Pch transistor TP3, a plural number of sense amplifiers SA and an Nch transistor TN1.
A node SAP, operating as a positive power supply of the sense amplifier SA, is driven by the overdrive circuit 1 and by a Pch transistor TP3. The overdrive circuit 1 is controlled by a control signal SEP1, while the Pch transistor TP3 is driven by an array voltage VARY, and has its gate supplied with a control signal SEP2. A node SAN, operating as the ground for the sense amplifiers SA, is driven by an Nch transistor TN1, to the gate of which is transmitted a control signal SEN. The sense amplifier SA is made up of two Pch transistors and two Nch transistors, and actuates bitlines BLT, BLN. There are bitline capacitances Cd, parasitic on the bitlines BLT, BLN, respectively.
To the overdrive circuits 1 of the sub-arrays A, B, . . . , a power supply VDD is supplied as power supply. It is noted that a wiring resistance R is parasitic on the wiring from a pad of the power supply VDD to the overdrive circuit 1, and a power supply VDD1 is transmitted via wiring resistance R to the overdrive circuit 1. The resistance value of the wiring resistance R differs from one bank to another by such factors as varying distances from the pad.
FIG. 14 depicts a circuit diagram showing the constitution of the conventional overdrive circuit 1 used in FIG. 13. The conventional overdrive circuit 1 includes a Pch transistor TP100, having a source and a drain connected to a power supply VDD1 and to a node SAP and having a gate supplied with a control signal SEP1.
FIG. 15 depicts a timing chart showing the operation of the circuits shown in FIGS. 13 and 14. It is assumed that, out of the plural sub-arrays, only the sub-array A is activated to perform the sensing operation. In FIG. 15, the levels of the control signals SEP1, SEP2 and SEN and voltage waveforms of the power supply VDD1, nodes SAP and SAN and the bitlines BLT, BLN, are indicated by solid lines.
Before timing T1, the potentials of the nodes SAP and SAN and the bitlines BLT, BLN are set to one-half of the array voltage VARY (0.5×VARY), and wordlines, not shown, are activated to read out the memory cell information. There is generated an extremely small differential potential between the bitlines BLT and BLN.
At a timing T1, the control signal SEP1 goes LOW (VSS) from HIGH (VDD). This turns the Pch transistor PT100 on so that the node SAP is driven towards the power supply VDD1. This generates a current flow from the power supply VDD so that the potential of the power supply VDD1 is transiently lowered by the wiring resistance R. On the other hand, the control signal SEN is changed from LOW to HIGH at timing T1. This turns the Nch transistor TN1 on so that the node SAN is driven towards the voltage VSS (ground). Since the nodes SAP and SAN are driven, the sense amplifier SA is activated, so that the bitlines BLT and BLN become HIGH and LOW, respectively, to commence the sensing operation.
At timing T3, the potential of the bitline BLT has risen to the potential of the array voltage VARY. At timing T3, the control signals SEP1 and SEP2 are set to HIGH and LOW levels, respectively. This turns the Pch transistor TP100 and the Pch transistor TP3 off and on, respectively, and hence the node SAP is driven by the array voltage VARY.
The time period from timing T1 to timing T3 is termed an overdrive period. During this time period, the sense amplifiers SA is driven by a high voltage, which is the power supply VDD, so that, even if the array voltage VARY is a lower voltage, the sense operation can be carried out at a higher speed.
On the other hand, the overdrive circuit 1 supplies a large amount of electrical charges to the node SAP during the overdrive period. The reason the large amount of electrical charges is supplied is that the sub-array A includes a large number of sense amplifiers SA, and that the capacitance Cd of the bitlines, sensed to the high level
side, has to be set to a value VARY from 0.5×VARY. With the number N of the sense amplifiers SA of the sub-array, the total load capacitance CD=N×Cd. The electrical charges QD, supplied to the node SAP, may be represented by the following equation (1):QD=CD×0.5×VARY  (1)
It is seen from FIG. 15 that, since the large amount of the electrical charges flows through the wiring resistance R1, the voltage of the power supply VDD1 sags from the power supply VDD by voltage drop during the overdrive period.
As a related technology, a semiconductor memory, in which high-speed sense amplifier operation for coping with the use of a lower voltage and improved reliability of the memory cell capacitors may be achieved in combination, is shown in Patent Document 1.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2002-230975A, the disclosure thereof being incorporated herein by reference thereto.
This disclosure maybe also referred to upon needs in the present invention when analyzing the nature of operation as set forth below.